SI5347 Datasheet, PDF (6/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 3. Input Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ Max
Standard Differential or Single-Ended/LVCMOS — AC-coupled (IN0, IN1, IN2, IN3/FB_IN)
Input Frequency Range f_{IN_DIFF}
Differential
0.008
—
750
Single-ended/LVCMOS 0.008
—
250
Input Voltage Swing
V_{IN_DIFF} f_IN< 250 MHz, Differential 100
250 MHz < f_IN< 750 MHz, 225
Differential
—
1800
—
1800
Input Voltage Amplitude
V_{IN_SE}
f_IN< 250 MHz, Single-
100
ended
—
3600
Unit
MHz
mVpp_se
mVpp_se
mVpp_se
Slew Rate^1,2
SR
400
—
—
V/µs
Duty Cycle
DC
40
—
60
%
Capacitance
C_IN
Pulsed CMOS — DC-coupled (IN0, IN1, IN2, IN3)³
—
2
—
pF
Input Frequency
Input Voltage
Slew Rate^1,2
f_{IN_-}
PULSED
V_IL
V_IH
SR
0.008
—
250
–0.2
—
0.33
0.49
—
—
400
—
—
MHz
V
V
V/µs
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
ns
Input Resistance
R_IN
REFCLK (Applied to XA/XB)
—
8
—
k
REFCLK Frequency
f_{IN_REF} Frequency range for best
48
output jitter performance
—
54
MHz
Input Voltage Swing
Slew rate^1,2
V_{IN_DIFF}
365
V_{IN_SE}
365
SR Imposed for best jitter per- 400
formance
—
2500 mVpp_diff
—
2000 mVpp_se
—
—
V/µs
Input Duty Cycle
DC
40
—
60
%
Notes:
1. Imposed for jitter performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 - 0.2) x V_{IN_Vpp_se}) / SR.
3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled
because they have a duty cycle significantly less than 50%. A typical application example is a low frequency video
frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.33 and 0.49 V, respectively),
refer to the input attenuator circuit for DC-coupled Pulsed LVCMOS in the Si5347-46 Family Reference Manual.
Otherwise, for standard LVCMOS input clocks, use the Standard AC-coupled, Single-ended input mode.
6
Rev. 1.1