SI5347 Datasheet, PDF (40/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
5.8.8. LVCMOS Output Signal Swing
The signal swing (V_OL/V_OH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output
driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. Each output
driver automatically detects the voltage on the VDDO pin to properly determine the correct output voltage.
5.8.9. LVCMOS Output Polarity
When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTx). By
default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTx pin.
The polarity of these clocks is configurable, which enables complementary clock generation and/or inverted
polarity with respect to other output drivers.
5.8.10. Output Enable/Disable
The Si5347/46 allows enabling/disabling outputs by pin or register control, or a combination of both. Two output
enable pins are available (OE0, OE1). The output enable pins can be mapped to any of the outputs (OUTx)
through register configuration. By default OE0 controls all of the outputs while OE1 remains unmapped and has no
effect until configured. Figure 27 shows an example of an output enable mapping scheme that is register
configurable and can be stored in NVM as the default at power-up.
Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output
when the OE pin(s) has them enabled. By default the output enable register settings are configured to allow the OE
pins to have full control.
DSPLL
A
Output
Crosspoint
Si5346
A
B
÷R₀
OUT0
OUT0
DSPLL
B
A
B
÷R₁
A
B
÷R₂
A
B
÷R₃
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OE0
OE1
DSPLL
A
Output
Crosspoint
A
B
Si5346
÷R₀
OUT0
OUT0
A
B
÷R₁
DSPLL
B
A
B
÷R₂
A
B
÷R₃
OUT1
OUT1
OE0
OUT2
OUT2
OUT3
OUT3
OE1
In its default state the OE0 pin enables/
disables all outputs. The OE1 pin is not
mapped and has no effect on outputs.
An example of a configurable output enable
scheme. In this case OE0 controls the outputs
associated with DSPLL A, while OE1 controls
the outputs of DSPLL B.
Figure 27. Example of Configuring Output Enable Pins
5.8.11. Output Disable During LOL
By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode.
There is an option to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream
PLL into holdover.
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Rev. 1.1