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SI5347 Datasheet, PDF (11/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS | |||
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Si5347/46
Table 6. LVCMOS Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = â40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Output Frequency
fOUT
0.0001 â 250 MHz
Duty Cycle
DC
fOUT <100 MHz
47 â 53 %
100 MHz < fOUT < 250 MHz
44 â 55
Output-to-Output Skew
TSK
Output Voltage High1, 2, 3 VOH
LVCMOS outputs
â
VDDO = 3.3 V
â 100 ps
OUTx_CMOS_DRV=1
IOH = â10 mA VDDO x â
â
V
0.75
OUTx_CMOS_DRV=2
IOH = â12 mA
ââ
OUTx_CMOS_DRV=3
IOH = â17 mA
ââ
VDDO = 2.5 V
OUTx_CMOS_DRV=1
IOH = â6 mA VDDO x â
â
V
OUTx_CMOS_DRV=2
0.75
IOH = â8 mA
ââ
OUTx_CMOS_DRV=3
IOH = â11 mA
ââ
VDDO = 1.8 V
OUTx_CMOS_DRV=2
IOH = â4 mA VDDO x â
â
0.75
V
OUTx_CMOS_DRV=3
IOH = â5 mA
ââ
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Si5347/46 Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
Zs
VOL/VOH
IOL/IOH
IDDO
OUT
OUT
LVCMOS Output Test Configuration
Trace length 5
inches
50
499 ï
0.1 µF
4.7 pF
56 ï
50 ï Scope Input
499 ï
0.1 µF
50
50 ï Scope Input
4.7 pF
56 ï
Rev. 1.1
11
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