SI5347 Datasheet, PDF (46/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 17. Si5347/46 Pin Descriptions¹
Pin
Name
Pin Number
Si5347A/B Si5347C/D Si5346
Pin
Type²
Function
Inputs
XA
8
XB
9
8
5
I Crystal Input. Input pin for external crystal (XTAL). Alternatively
9
6
I
these pins can be driven with an external reference clock (REF-
CLK). An internal register bit selects XTAL or REFCLK mode.
Default is XTAL mode.
X1
7
7
4
I XTAL Ground. Connect these pins directly to the XTAL ground
X2
10
10
7
I
pins. X1, X2, and the XTAL ground pins should be separated from
the PCB ground plane. Refer to the Si5347/46 Family Reference
Manual for layout guidelines. These pins should be left discon-
nected when connecting XA/XB pins to an external reference clock
(REFCLK).
IN0
63
63
43
I Clock Inputs. These pins accept an input clock for synchronizing
IN0
64
64
44
I
the device. They support both differential and single-ended clock
signals. Refer to “5.6.4. Input Configuration and Terminations” for
IN1
1
1
1
I _{input termination options. These pins are high-impedance and must}
IN1
2
2
2
I ^{be terminated externally. The negative side of the differential input}
must be grounded when accepting a single-ended clock.
IN2
14
14
10
I
IN2
15
15
11
I
IN3
61
61
41
I
IN3
62
62
42
I
Notes:
1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names.
2. I = Input, O = Output, P = Power.
3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
46
Rev. 1.1