SI5347 Datasheet, PDF (32/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
5.6.7. Synchronizing to Gapped Input Clocks
Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped
clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing
some of its cycles. Gapping a clock severely increases its jitter, so a phase-locked loop with high jitter tolerance
and low loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic non-
gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of
100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is
shown in Figure 16.
Gapped Input Clock
100 MHz clock
1 missing period every 10
Periodic Output Clock
90 MHz non-gapped clock
100 ns
100 ns
1 2 3 4 5 6 7 8 9 10
DSPLL
123456789
10 ns
Period Removed
11.11111... ns
Figure 16. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out
of every 8. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching
between gapped clocks may violate the hitless switching specification in Table 8 when the switch occurs during a
gap in either input clock.
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Rev. 1.1