SI5347 Datasheet, PDF (30/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

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5.6. Inputs (IN0, IN1, IN2, IN3)
There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and
single-ended clocks. A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of
the DSPLLs as shown in Figure 14.
Si5347
Input
Crosspoint
IN0
IN0
÷
P_0n
P_0d
0
1
2
3
DSPLL
A
IN1
IN1
÷
P_1n
P_1d
0
1
DSPLL
2
B
3
IN2
÷ ^P2n
IN2
P_2d
0
1
DSPLL
2
C
3
IN3
IN3
÷
P_3n
P_3d
0
1
DSPLL
2
D
3
Figure 14. DSPLL Input Selection Crosspoint
5.6.1. Input Selection
Input selection for each of the DSPLLs can be made manually through register control or automatically using an
internal state machine.
5.6.2. Manual Input Selection
In Manual Mode, the input selection is made by writing to a register. If there is no clock signal on the selected input,
the DSPLL will automatically enter Holdover Mode.
5.6.3. Automatic Input Selection
When configured in this mode, the DSPLL automatically selects a valid input that has the highest configured
priority. The priority scheme is independently configurable for each DSPLL and supports revertive or non-revertive
selection.
All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). Only inputs
that do not assert both the LOS and OOF monitors can be selected for synchronization by the automatic state
machine. The DSPLL(s) will enter the Holdover mode if there are no valid inputs available.
5.6.4. Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination
schemes are shown in Figure 15. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle
Pulsed CMOS signals can be dc-coupled. Unused inputs can be disabled and left unconnected when not in use.
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Rev. 1.1