SI5347 Datasheet, PDF (14/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 8. Performance Characteristics
(V_DD = 1.8 V ±5%, or 3.3 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
PLL Loop Bandwidth
Programming Range³
Initial Start-Up Time
f_BW
0.1 — 4000 Hz
t_START
Time from power-up to when the
— 30 45
ms
device generates free-running clocks
PLL Lock Time
t_ACQ
With Fastlock enabled,
f_IN = 19.44 MHz¹
— 500 600
ms
POR to Serial Interface
Ready²
t_RDY
—
—
15
ms
Jitter Peaking
J_PK
Measured with a frequency plan run- —
— 0.1
dB
ning a 25 MHz input, 25 MHz output,
and a loop bandwidth of 4 Hz
Jitter Tolerance
J_TOL
Compliant with G.8262 Options 1&2 — 3180 — UI pk-pk
Carrier Frequency = 10.3125 GHz
Jitter Modulation Frequency = 10 Hz
Maximum Phase
Transient During a
Hitless Switch
t_SWITCH Only valid for a single switch between —
—
2.8
ns
two input clocks running at the same
frequency
Pull-in Range
_P
— 500 —
ppm
Input-to-Output Delay
Variation
RMS Phase Jitter⁴
t_IODELAY
J_GEN
12 kHz to 20 MHz
—
2
—
ns
— 0.090 0.165 ps RMS
Notes:
1. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this
case, lock time was measured with nominal and fastlock bandwidths, both set to 100 Hz, LOL set/clear thresholds of 3/
0.3 ppm respectively, using IN0 as clock reference by removing the reference and enabling it again, then measuring the
delta time between the first rising edge of the clock reference and the LOL indicator de-assertion.
2. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to
commands.
3. Actual loop bandwidth might be lower; please refer to CBPro for actual value on your frequency plan.
4. Jitter generation test conditions: f_IN = 19.44 MHz, f_OUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz.
Does not include jitter from input reference.
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Rev. 1.1