SI5347 Datasheet, PDF (31/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Standard AC‐coupled Differential LVDS
50
3.3 V, 2.5 V
50
LVDS or CML
INx
100
INx
Si5347/46
Standard
Pulsed CMOS
3.3 V, 2.5 V
LVPECL
Standard AC‐coupled Differential LVPECL
Si5347/46
50
INx
Standard
100
INx
50
Pulsed CMOS
Standard AC‐coupled Single‐ended
50
3.3 V, 2.5 V, 1.8 V
LVCMOS
Si5347/46
INx
Standard
INx
Pulsed CMOS
Pulsed CMOS DC‐coupled Single‐ended
R1
INx
50
3.3 V, 2.5 V, 1.8 V
R2
INx
LVCMOS
VDD R1 () R2 ()
1.8V
549
442
Resistor values for _2.5V
680
324
fIN_PULSED < 1 MHz
3.3V
750
243
Si5347/46
Standard
Pulsed CMOS
Figure 15. Termination of Differential and LVCMOS Input Signals
5.6.5. Hitless Input Switching
Hitless switching is a feature that prevents a phase transient from propagating to the output when switching
between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input
frequencies are frequency locked, meaning that they have to be exactly at the same frequency, or at a fractional
frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase
difference between the two input clocks during an input switch. When disabled, the phase difference between the
two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching
feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be
enabled on a per DSPLL basis.
5.6.6. Glitchless Input Switching
The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The
DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if
it is enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency.
There will be no output runt pulses generated at the output during the transition.
Rev. 1.1
31