SI5347 Datasheet, PDF (15/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 9. I²C Timing Specifications (SCL,SDA)
Parameter
Symbol
SCL Clock
f_SCL
Frequency
SMBus Timeout
—
Hold Time (repeated)
START Condition
Low Period of the SCL
Clock
HIGH Period of the SCL
Clock
Set-up Time for a
Repeated START Condi-
tion
Data Hold Time
Data Set-up Time
Rise Time of Both SDA
and SCL Signals
Fall Time of Both SDA and
SCL Signals
Set-up Time for STOP
Condition
Bus Free Time between a
STOP and START Condi-
tion
Data Valid Time
Data Valid Acknowledge
Time
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_r
t_f
t_SU:STO
t_BUF
t_VD:DAT
t_VD:ACK
Test Condition
When Timeout is
Enabled
Standard Mode
100 kbps
Min
Max
—
100
Fast Mode
400 kbps
Min
Max
—
400
25
35
25
35
4.0
—
0.6
—
4.7
—
1.3
—
4.0
—
0.6
—
4.7
—
0.6
—
100
—
100
—
250
—
100
—
—
1000
20
300
—
300
—
300
4.0
—
0.6
—
4.7
—
1.3
—
—
3.45
—
0.9
—
3.45
—
0.9
Unit
kHz
ms
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
Rev. 1.1
15