SI5347 Datasheet, PDF (35/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

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5.7.4. LOL Detection
There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts an LOL register bit when a DSPLL has
lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of
lock condition for each of the DSPLLs (LOL_A, LOL_B, LOL_C, LOL_D). The LOL monitor functions by measuring
the frequency difference between the input and feedback clocks at the phase detector. There are two LOL
frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An
optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely
lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the
DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in Figure 21. The live LOL register
always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin
reflects the current state of the LOL monitor.
Si5347
Sticky
LOL StatuLsORSegisters
Live
LOL Monitor
LOL
Clear
t
LOL
Set
DSPLL D
DSPLL C
DSPLL B
DSPLL A
fIN
DSPLL A
PD LPF
÷M
LOL_D
LOL_C
LOL_B
LOL_A
Figure 21. LOL Status Indicators
Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to
10000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status.
An example configuration where LOCK is indicated when there is less than 0.2 ppm frequency difference at the
inputs of the phase detector and LOL is indicated when there is more than 2 ppm frequency difference is shown in
Figure 22.
LOL
LOCKED
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
Hysteresis
Lost Lock
0
0.2
2
Phase Detector Frequency Difference (ppm)
Figure 22. LOL Set and Clear Thresholds
20,000
Rev. 1.1
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