SI5347 Datasheet, PDF (36/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to
completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering
as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and
loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilderPro utility.
5.7.5. Interrupt Pin (INTR)
An interrupt pin (INTR) indicates a change in state with any of the status indicators for any of the DSPLLs. All
status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by
clearing the sticky status registers.
IN0_LOS_STKY
IN0_OOF_STKY
IN1_LOS_STKY
IN1_OOF_STKY
IN2_LOS_STKY
IN2_OOF_STKY
IN3_LOS_STKY
IN3_OOF_STKY
mask
mask
mask
mask
mask
mask
mask
mask
XAXB_LOS_STKY
mask
LOLA_STKY
LOLB_STKY
LOLC_STKY
LOLD_STKY
mask
mask
mask
mask
HOLDA_STKY
HOLDB_STKY
HOLDC_STKY
HOLDD_STKY
mask
mask
mask
mask
IN0
IN1
IN2
IN3
LOL
HOLD
Figure 23. Interrupt Triggers and Masks
INTR
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Rev. 1.1