SI5347 Datasheet, PDF(50/59 Page) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

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SI5347 Datasheet, PDF (50/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

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Si5347/46

Table 17. Si5347/46 Pin Descriptions1 (Continued)

Name

Pin Number

Si5347A/B Si5347C/D Si5346

Type2

Function

FDEC

I Frequency Decrement Pin (Si5347 only). This pin is used to step-

down the output frequency of a selected DSPLL. The frequency

change step size is register configurable. The DSPLL that is

affected by the frequency change is determined by the DSPLL_-

SEL[1:0] pins. See Note 4. This pin must be pulled up or down

externally (do not leave floating when not in use).

FINC

I Frequency Increment Pin (Si5347 only). This pin is used to step-

up the output frequency of a selected DSPLL. The frequency

change step size is register configurable. The DSPLL that is

affected by the frequency change is determined by the DSPLL_-

SEL[1:0] pins. See Note 3. This pin is pulled low internally and can

be left unconnected when not in use.

RSVD

â Reserved. These pins are connected to the die. Leave discon-

â nected.

â No Connect. These pins are not connected to the die. Leave dis-

connected.

Notes:

1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names.

2. I = Input, O = Output, P = Power.

3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.

Rev. 1.1

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