SI5347 Datasheet, PDF (41/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
5.8.12. Output Disable During XAXB_LOS
The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for
the operation of the DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default
all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs
enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault
condition.
5.8.13. Output Driver State When Disabled
The disabled state of an output driver is register configurable as disable low, disable high, or disable high-
impedance.
5.8.14. Synchronous/Asynchronous Output Disable
Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output
will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from
occurring when disabling an output. In asynchronous disable mode, the output clock will disable immediately
without waiting for the period to complete.
5.8.15. Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures
consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or
asserting the hard reset bit will have the same result.
5.9. Power Management
Unused inputs, output drivers, and DSPLLs can be powered down when unused. Consult the Si5347/46 Family
Reference Manual and ClockBuilder Pro configuration utility for details.
5.10. In-Circuit Programming
The Si5347/46 is fully configurable using the serial interface (I²C or SPI). At power-up the device downloads its
default register values from internal non-volatile memory (NVM). Application specific default configurations can be
written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to
NVM is in-circuit programmable with normal operating power supply voltages applied to its V_DD and V_DDA pins. The
NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer
accessible. Refer to the Si5347/46 Family Reference Manual for a detailed procedure for writing registers to NVM.
5.11. Serial Interface
Configuration and operation of the Si5347/46 is controlled by reading and writing registers using the I²C or SPI
interface. The I2C_SEL pin selects I²C or SPI operation. Communication with both 3.3 V and 1.8 V host is
supported. The SPI mode operates in either 4-wire or 3-wire mode. See the Si5347/46 Family Reference Manual
for details.
5.12. Custom Factory Preprogrammed Parts
For applications where a serial interface is not available for programming the device, custom pre-programmed
parts can be ordered with a specific configuration written into NVM. A factory pre-programmed part will generate
clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part
number wizard (www.silabs.com/clockbuilderpro) to quickly and easily request and generate a custom part number
for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum
matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum,
simply place an order with your local Silicon Labs sales representative. Samples of your pre-programmed device
will typically ship in about two weeks.
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