SI5347 Datasheet, PDF (17/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 10. SPI Timing Specifications (4-Wire)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Delay Time, CS Rise to SDO Tri-State
Setup Time, CS to SCLK
Hold Time, SCLK Fall to CS
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CS)
f_SPI
—
—
20
MHz
T_DC
40
—
60
%
T_C
50
—
—
ns
T_D1
—
—
18
ns
T_D2
—
—
15
ns
T_D3
—
—
15
ns
T_SU1
5
—
—
ns
T_H1
5
—
—
ns
T_SU2
5
—
—
ns
T_H2
5
—
—
ns
T_CS
2
—
—
T_C
SCLK
CS
SDI
SDO
TSU1
T_D1
TSU2
TH2
T_D2
T_C
TH1
TCS
T_D3
Figure 3. 4-Wire SPI Serial Interface Timing
Rev. 1.1
17