SI5347 Datasheet, PDF (33/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
5.7. Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3) are monitored for LOS and OOF as shown in Figure 17. The reference at
the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the
DSPLLs also has an LOL indicator, which is asserted when synchronization is lost with their selected input clock.
Si5347
XA XB
OSC
IN0
IN0
÷
P0n
P0d
LOS OOF ^Precision
Fast
IN1
IN1
÷
P1n
P1d
LOS
OOF ^Precision
Fast
IN2
IN2
÷
P_2n
P_2d
LOS OOF ^Precision
Fast
IN3
IN3
÷
P3n
P_3d
LOS
OOF ^Precision
Fast
LOS
LOL ^{DSPLL A}
PD LPF
÷M
LOL ^{DSPLL B}
PD LPF
÷M
LOL ^{DSPLL C}
PD LPF
÷M
LOL ^{DSPLL D}
PD LPF
÷M
Figure 17. Si5347 Fault Monitors
5.7.1. Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing
clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing
edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS
status for each of the monitors is accessible by reading a status register. The live LOS register always displays the
current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS
monitors is also available.
Monitor
LOS
en
LOLOSS
Live
Sticky
Figure 18. LOS Status Indicators
Rev. 1.1
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