SI5347 Datasheet, PDF (47/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 17. Si5347/46 Pin Descriptions¹ (Continued)
Pin
Name
Pin Number
Si5347A/B Si5347C/D Si5346
Pin
Type²
Function
Outputs
OUT0
24
OUT0
23
OUT1
31
OUT1
30
OUT2
35
24
20
O Output Clocks. These output clocks support a programmable sig-
23
19
O ^{nal amplitude and common mode voltage. Desired output signal for-}
mat is configurable using register control. Termination
38
25
O _{recommendations are provided in “5.8.2. Differential Output Termi-}
37
24
O ^{nations” and “5.8.3. LVCMOS Output Terminations” Unused out-}
puts should be left unconnected.
45
31
O
OUT2
34
44
30
O
OUT3
38
51
36
O
OUT3
37
50
35
O
OUT4
45
—
—
O
OUT4
44
—
—
O
OUT5
51
—
—
O
OUT5
50
—
—
O
OUT6
54
—
—
O
OUT6
53
—
—
O
OUT7
59
—
—
O
OUT7
58
—
—
O
Notes:
1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names.
2. I = Input, O = Output, P = Power.
3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
Rev. 1.1
47