SI5347 Datasheet, PDF (58/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.95
 Removed advanced product information revision
history.
 Updated Ordering Guide and changed references to
revision B.
 Updated parametric tables 2,3,5,6,7,8 to reflect
production characterization release.
 Updated terminology to align with ClockBuilder Pro
software.
 Corrected Table 3 references and specifications from
"LVCMOS — DC-coupled" to "Pulsed CMOS — DC-
coupled".
 Corrected Table 9: I²C data hold time specification to
100 ns from 5 µs.
Revision 0.95 to Revision 1.0
 Added 4-Output Si5347C and Si5347D grade
devices to the data sheet.
 Corrected AC Test Configuration schematic in Tables
2 and 6.
 Corrected minimum input frequency down to
0.008 MHz in Table 3.
 Corrected XAXB VIN_DIFF minimum input voltage
swing in Table 3.
 Corrected VIN input voltage swing and split into
VIN_DIFF and VIN_SE for differential and single-
ended inputs in Table 3.
 Added FINC/FDEC maximum update rates of 1 MHz
in Table 4.
 Added common-mode voltage for 1.8 V sub-LVDS in
Table 5.
 Added typical crosstalk spec for Si5346 in Table 5.
 Updated TSK, output-to-output skew, in Table 5.
 Updated ZO, differential output impedance for Low
Power Mode in Table 5.
 Updated LVPECL VOUT maximum value in Table 5.
 Adjusted LVCMOS VOH specification in Table 6.
 Corrected tSTART, tACQ, and tRDY in Table 8.
 Updated SPI timing diagrams and specifications and
removed SPI rise/fall time in Tables 10 and 11.
Revision 1.0 to Revision 1.1
 Corrected Si5347C/D pin list numbers in Table 17 to
match the pinout.
58
Rev. 1.1