SI5347 Datasheet, PDF (5/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Output Buffer Supply Current
Total Power Dissipation
Symbol
I_DDO
P_d
Test Condition
Min
LVPECL Output³
—
@ 156.25 MHz
LVDS Output³
—
@ 156.25 MHz
3.3V LVCMOS⁴ output —
@ 156.25 MHz
2.5V LVCMOS⁴ output —
@ 156.25 MHz
1.8V LVCMOS⁴ output —
@ 156.25 MHz
Si5347 Note ^1,5
—
Si5346 Note ^2,5
—
Typ Max Unit
21
25
mA
15
18
mA
21
25
mA
16
18
mA
12
13
mA
980 1160 mW
840 1000 mW
Notes:
1. Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Differential outputs terminated into an AC coupled 100  load.
4. LVCMOS outputs measured into a 5-inch 50  PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5347/46 Family Reference Manual for
more details on register settings.
5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Differential Output Test Configuration
IDDO
OUT
OUT
50
0.1 µF
IDDO
100
OUT
50
0.1 µF
OUT
LVCMOS Output Test Configuration
Trace length 5
inches
50
499 
0.1 µF
4.7 pF
56 
50  Scope Input
499 
0.1 µF
50
50  Scope Input
4.7 pF
56 
Rev. 1.1
5