SI5347 Datasheet, PDF (49/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
Table 17. Si5347/46 Pin Descriptions¹ (Continued)
Pin
Name
Pin Number
Si5347A/B Si5347C/D Si5346
Pin
Type²
Function
Control/Status
INTR
12
12
17
O Interrupt. This pin is asserted low when a change in device status
has occurred. It should be left unconnected when not in use. See
Note ³.
RST
6
6
3
I _{Device Reset. Active low input that performs power-on reset (POR)}
of the device. Resets all internal logic to a known state and forces
the device registers to their default values. Clock outputs are
disabled during reset. This pin is internally pulled-up. See Note ³.
OE0
11
11
12
I Output Enable 0. This pin is used to enable (when held low) and
disable (when held high) the output clocks. By default this pin con-
trols all outputs. It can also be configured to control a subset of out-
puts. See section “5.8.10. Output Enable/Disable” for details. This
pin is internally pulled-down. See Note ³.
OE1
41
41
—
Output Enable 1. (Si5347) This is an additional output enable pin
that can be configured to control a subset of outputs. By default it
has no control on the outputs until configured. See section “5.8.10.
Output Enable/Disable” for details. There is no internal pull-up/pull-
down for this pin. See Note ⁴. This pin must be pulled up or down
externally (do not leave floating when not in use).
—
—
37
Output Enable 1. (Si5346) This is an additional output enable pin
that can be configured to control a subset of outputs. By default it
has no control on the outputs until configured. See section “5.8.10.
Output Enable/Disable” for details. This pin is internally pulled-
down. See Note ³.
LOL_A
3
LOL_B
4
LOL_C
5
LOL_D
47
3
28
O Loss Of Lock_A/B/C/D. These output pins indicate when DSPLL
4
27
O
A, B, C, D is out-of-lock (low) or locked (high). They can be left
unconnected when not in use. Si5347: See Note ³, Si5346: See
5
—
O _Note ⁴_.
47
—
O
LOS_X-
25
AXB
25
33
O Status Pins. This pin indicates a loss of signal alarm on the XA/XB
pins. This either indicates a XTAL failure or a loss of external signal
on the XA/XB pins. This pin can be left unconnected when unused.
Si5347: See Note ³, Si5346: See Note ³.
DSPLL_-
26
SEL0
DSPLL_-
27
SEL1
26
—
I DSPLL Select Pins (Si5347 only). These pins are used in conjunc-
tion with the FINC and FDEC pins. The DSPLL_SEL[1:0] pins deter-
27
—
I
mine which DSPLL is affected by a frequency change using the
FINC and FDEC pins. See section “5.4. Digitally-Controlled Oscilla-
tor (DCO) Mode” for details. These pins are internally pulled-down.
See Note ³.
Notes:
1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names.
2. I = Input, O = Output, P = Power.
3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
Rev. 1.1
49