SI5347 Datasheet, PDF (55/59 Pages) Silicon Laboratories – DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

Si5347/46
10. PCB Land Pattern
Figure 31 illustrates the PCB land pattern details for the devices. Table 20 lists the values for the dimensions
shown in the illustration. Refer to the Si5347-46 Family Reference Manual for information about thermal via
recommendations.
Si5347
Si5346
Figure 31. PCB Land Pattern
Table 20. PCB Land Pattern Dimensions
Dimension
Si5347 (Max)
Si5346 (Max)
C1
8.90
6.90
C2
8.90
6.90
E
0.50
0.50
X1
0.30
0.30
Y1
0.85
0.85
X2
5.30
5.30
Y2
5.30
5.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication
Allowance of 0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste
release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
8. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.1
55