K5D5657DCM-F015 Datasheet, PDF (8/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Figure 1. NAND Flash(x8) ARRAY ORGANIZATION
Preliminary
MCP MEMORY
1 Block =32 Pages
= (16K + 512) Byte
64K Pages
(=2,048 Blocks)
1st half Page Register 2nd half Page Register
(=256 Bytes)
(=256 Bytes)
512Byte
16 Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
8 bit
Page Register
512 Byte
16 Byte
I/O 0 ~ I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle A17
A18
A19
A20
A21
A22
A23
A24
NOTE: 1. Column Address : Starting Address of the Register.
2. 00h Command(Read) : Defines the starting address of the 1st half of the register.
3. 01h Command(Read) : Defines the starting address of the 2nd half of the register.
4. A8 is set to "Low" or "High" by the 00h or 01h Command.
5. The device ignores any additional input of address cycles than reguired.
Column Address
Row Address
(Page Address)
-8-
Revision 0.0
June 2003