K5D5657DCM-F015 Datasheet, PDF (41/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
D. DEVICE OPERATIONS
ADDRESSES of 256Mb
ADDRESSES of 512Mb
BANK ADDRESSES (BA0 ~ BA1)
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
: In case x 16
This SDRAM is organized as four independent banks of
4,194,304 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
This SDRAM is organized as four independent banks of
8,388,608 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
: In case x 32
: In case x 32
This SDRAM is organized as four independent banks of
2,097,152 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
This SDRAM is organized as four independent banks of
4,194,304 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA0 ~ BA1 dur-
ing read or write command.
: In case x 32
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
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Revision 0.0
June 2003