K5D5657DCM-F015 Datasheet, PDF (69/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
Burst Read Single bit Write Cycle @Burst Length=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note 2
ADDR
RAa
CAa RBb CAb
RCc
CBc
CCd
BA0
BA1
A10/AP
RAa
RBb
RCc
{^CL=2
DQ
CL=3
DAa0
DAa0
QAb0 QAb1
QAb0 QAb1
DBc0
DBc0
QCd0 QCd1
QCd0 QCd1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
Read with
(A-Bank) Auto Precharge
(A-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Write with
Auto Precharge
(B-Bank)
*NOTE:
1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
Precharge
(C-Bank)
: Don’t care
- 69 -
Revision 0.0
June 2003