K5D5657DCM-F015 Datasheet, PDF (3/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
Multi-Chip Package MEMORY
256M Bit (32Mx8) Nand Flash / 256M Bit (4Mx16x4Banks) Mobile SDRAM
FEATURES
<Common>
• Operating Temperature : -25°C ~ 85°C
• Package : 107-ball FBGA Type - 10.5x13mm, 0.8mm pitch
<NAND>
• Power Supply Voltage : 2.4~2.9V
• Organization
- Memory Cell Array : (32M + 1024K)bit x 8bit
- Data Register : (512 + 16)bit x 8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• Page Read Operation
- Page Size : (512 + 16)Byte
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
<Mobile SDRAM>
• Power Supply Voltage : 1.65~1.95V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
GENERAL DESCRIPTION
The K5D5657DCM is a Multi Chip Package Memory which combines 256Mbit Nand Flash Memory and 256Mbit synchronous high
data rate Dynamic RAM.
256Mbit NAND Flash memory is organized as 32M x8 bits and 256Mbit SDRAM is organized as 4M x16 bits x4 banks.
In 256Mbit NAND Flash, a 528-Byte page program can be typically achieved within 200us and an 16K-Byte block erase can be typi-
cally achieved within 2ms. In serial read operation, a byte can be read by 50ns. DQ pins serve as the ports for address and data
input/output as well as command inputs. Even the write-intensive systems can take advantage of FLASH′s extended reliability of
100K program/erase cycles with real time mapping-out algorithm. These algorithms have been implemented in many mass storage
applications.
In 256Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
The K5D5657DCM is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption. This device is available in 107-ball FBGA Type.
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Revision 0.0
June 2003