K5D5657DCM-F015 Datasheet, PDF (59/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
tRC *Note 1
HIGH
RAS
CAS
*Note 2
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
{^CL=2
DQ
tRCD
CL=3
WE
Rb
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tOH
tSHZ *Note 4
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ _{*Note 4}
Db0 Db1 Db2 Db3
tRDL
Db0 Db1 Db2 Db3
tRDL
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
Write
(A-Bank) (A-Bank)
*NOTE:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Precharge
(A-Bank)
: Don’t care
- 59 -
Revision 0.0
June 2003