K5D5657DCM-F015 Datasheet, PDF (60/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note 2
ADDR
Ra
Ca
Cb
Cc
Cd
Rb
BA0
BA1
A10/AP
Ra
{^CL=2
DQ
tRCD
CL=3
WE
DQM
Rb
tRDL
Qa0 Qa1 Qb0 Qb1 Qb2
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
Dc0 Dc1 Dd0 Dd1
tCDL
tDAL
*Note 4
*Note 1
*Note 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
*NOTE:
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
4. tDAL ,last data in to active delay, is 2CLK + tRP.
Precharge
(A-Bank)
Row Active
(A-Bank)
: Don’t care
- 60 -
Revision 0.0
June 2003