K5D5657DCM-F015 Datasheet, PDF (35/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Auto refresh cycle time
Exit self refresh to active command
Col. address to col. address delay
Number of valid output data
Number of valid output data
Number of valid output data
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tARFC(min)
tSRFX(min)
tCCD(min)
CAS latency=3
CAS latency=2
CAS latency=1
Version
Unit
-IL
-15
19
30
ns
28.5
30
ns
28.5
30
ns
60
60
ns
100
us
88.5
90
ns
2
CLK
tRDL + tRP
-
1
CLK
1
CLK
105
ns
120
ns
1
CLK
2
1
ea
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum 3CLK of tDAL(= tRDL + tRP) is required because it need minimum 2CLK for tRDL and minimum 1CLK for tRP.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Note
1
1
1
1
1
2
3
2
2
4
5
- 35 -
Revision 0.0
June 2003