K5D5657DCM-F015 Datasheet, PDF (24/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyz-
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column
address[column 511/ 527 depending on the state of GND input pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0~A3 set the starting
address of the spare area while addresses A4~A7 are ignored in X8 device case. The Read1 command is needed to move the pointer
back to the main area. Figures6,7 show typical sequence and timings for each read operation.
Figure 6. Read1 Operation
CLE
CE
WE
ALE
R/B
RE
I/Ox
00h Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A24
tR
(00h Command)
Main array
Data Output(Sequential)
1)
(01h Command)
1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
NOTE :
1. After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
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Revision 0.0
June 2003