K5D5657DCM-F015 Datasheet, PDF (43/74 Pages) Samsung semiconductor – MCP Specification of 256Mb NAND and 256Mb Mobile SDRAM

K5D5657DCM-F015
Preliminary
MCP MEMORY
D. DEVICE OPERATIONS (continued)
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores the data for selecting driver
strength and partial self refresh. EMRS cycle is not mandatory
and the EMRS command needs to be issued only when DS or
PASR is used. The default state without EMRS command issued
is half driver strength and all 4 banks refreshed. The extended
mode register is written by asserting low on CS, RAS, CAS, WE
and high on BA1 ,low on BA0(The SDRAM should be in all bank
precharge with CKE already high prior to writing into the
extended mode register). The state of address pins A0 ~ A11 in
the same cycle as CS, RAS, CAS and WE going low is written in
the extended mode register. Two clock cycles are required to
complete the write operation in the extended mode register. The
mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as
all banks are in the idle state. A0 - A2 are used for partial self
refresh , A5 - A6 are used for Driver strength, "Low" on BA1 and
"High" on BA0 are used for EMRS. All the other address pins
except A0,A1,A2, BA1, BA0 must be set to low for proper EMRS
operation. Refer to the table for specific codes.
BANK ACTIVATE.
The bank activate command is used to select a random row in an
idle bank. By asserting low on RAS and CS with desired row and
bank address, a row access is initiated. The read or write opera-
tion can occur after a time delay of tRCD(min) from the time of
bank activation. tRCD is an internal timing parameter of SDRAM,
therefore it is dependent on operating clock frequency. The mini-
mum number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off the
result to the next higher integer.
The SDRAM has four internal banks in the same chip and shares
part of the internal circuitry to reduce chip area, therefore it
restricts the activation of four banks simultaneously. Also the
noise generated during sensing of each bank of SDRAM is high,
requiring some time for power supplies to recover before another
bank can be sensed reliably. tRRD(min) specifies the minimum
time required between activating different bank. The number of
clock cycles required between different bank activation must be
calculated similar to tRCD specification. The minimum time
required for the bank to be active to initiate sensing and restoring
the complete row of dynamic cells is determined by tRAS(min).
Every SDRAM bank activate command must satisfy tRAS(min)
specification before a precharge command to that active bank
can be asserted. The maximum time any bank can be in the
active state is determined by tRAS(max). The number of cycles for
both tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.
BURST READ
The burst read command is used to access burst of data on con-
secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read com-
mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command
is determined by the mode register which is already pro-
grammed. The burst read can be initiated on any column address
of the active row. The address wraps around if the initial address
does not start from a boundary such that number of outputs from
each I/O are equal to the burst length programmed in the mode
register. The output goes into high-impedance at the end of the
burst, unless a new burst read was initiated to keep the data out-
put gapless. The burst read can be terminated by issuing another
burst read or burst write in the same bank or the other active
bank or a precharge command to the same bank. The burst stop
command is valid at every page burst length.
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Revision 0.0
June 2003