K4C89183AF Datasheet, PDF (52/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
CAS Latency = 4 (Free Running QS mode)
CK
CK
Command
RDA
LAL
QS
DQ
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode
Data
Data 0
Data 1
Data 2
Data 3
Access Address
n
n+1
n+2
n+3
Burst Length
4 words(Address bits is LA1, LA0)
not carried from LA1~LA2
Functional Description (Continued)
• Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
Data
Data 0
Data 1
Data 2
Data 3
Access Address
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Burst Length
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
Addressing sequence for Interleave mode
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
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REV. 0.7 Jan. 2005