K4C89183AF Datasheet, PDF (17/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
6
7
t_CH
t_CL
t_CK
CK
CK
Input
(Control &
Addresses)
t_IS t_{IH LAL(after RDA)}
LDS/UDS
(Input)
CAS latency = 4
LQS/UQS
(Output)
DQ
(Output)
High-Z
8
9
10
11
12
13
14
15
16
17
18
DESL
t_CKQS
t_CKQS
t_CKQS
t_QSP t_QSP
t_LZ
t_QSQV
t_QSQ t_QSQ t_QSQV
Q0
t_AC
Q1 Q2
t_AC
t_AC
t_QSQ
t_HZ
Q3
t_OH
CAS latency = 5
LQS/UQS
(Output)
DQ
(Output)
High-Z
CAS latency = 6
LQS/UQS
(Output)
DQ
(Output)
High-Z
t_CKQS
t_CKQS
t_CKQS
t_QSP t_QSP
t_LZ
t_QSQV
t_QSQ t_QSQ t_QSQV
Q0
t_AC
Q1
Q2
t_AC
t_AC
t_QSQ
t_HZ
Q3
t_OH
t_CKQS
t_CKQS
t_CKQS
t_QSP t_QSP
t_LZ
t_QSQV
t_QSQ t_QSQ t_QSQV
Q0
t_AC
Q1
Q2
t_AC
t_AC
t_QSQ
t_HZ
Q3
t_OH
Note : DQ0 to DQ17 are aligned with LQS.
DQ18 to DQ35 are aligned with UQS.
LQS/UQS is always asserted in Free Running QS mode.
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REV. 0.7 Jan. 2005