K4C89183AF Datasheet, PDF (14/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.
2. Apply V_DD before or at the same time as V_DDQ.
3. Apply V_DDQ before or at the same time as V_REF.
4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.).
5. After stable power and clock, apply DESL and take PD = H.
6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1)
7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)
8. Issue two or more Auto-Refresh commands. (Note:1)
9. Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note : 1. Sequence 6, 7 and 8 can be issued in random order.
2. L=Logic Low, H = Logic High
V_DD
V_DDQ
V_REF
CLK
CLK
PD
Command
Address
DQ
2.5V(TYP)
1.8V(TYP)
0.9V(TYP)
200 µs(min)
t_PDEX
I_PDA
l_RSC
l_RSC
l_REFC
200 clock cycle(min)
l_REFC
DESL RDA MRS DESL RDA MRS DESL WRA REF DESL
op-code
op-code
WRA REF DESL
EMRS
MRS
DS
Hi-Z
QS
(Uni-QS mode)
QS
(Free Running mode)
EMRS
MRS
Low
Auto Refresh cycle Normal Operation
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REV. 0.7 Jan. 2005