K4C89183AF Datasheet, PDF (37/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Multiple Bank Write Timing (CL=4)
CLK
CLK
Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
l_RBD=2cycles
l_RBD=2cycles
l_RBD=2cycles
l_RBD=2cycles
l_RBD=2cycles
WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank
"a"
Unidirectional DS/QS mode
Bank
"b"
Bank
"a"
l_RC(Bank"a")=5cycles
l_RC(Bank"b")=5cycles
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
DS
(input)
QS
Low
(Output)
DQ
(Input)
WL=3
WL=3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DQ
(Input)
WL=3
WL=3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Note : l_RC to the same bank must be satisfied
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REV. 0.7 Jan. 2005