K4C89183AF Datasheet, PDF (45/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Mode Register Set Timing (CL=4, BL=4)
From Write operation to Mode Register Set operation
0
1
2
3
4
5
6
7
8
CLK
CLK
Command
WRA LAL
DESL
RDA MRS
9
10
11
12
13
14
15
l_RC=7cycles
DESL
RoDrA
WRA
LAL
A14~A0
UA
LA
Valid
(opcode)
UA
LA
BA0, BA1
BA
BA0="0"
BA1="0"
BA
WL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
DC
(input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DC
(input)
D0 D1 D2 D3
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
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REV. 0.7 Jan. 2005