K4C89183AF Datasheet, PDF (26/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Single Bank Read Timing (CL=5)
CLK
CLK
Command
Address
0
1
RDA LAL
l_RCD=1cycle
UA
LA
2
3
4
l_RC=6cycles
DESL
l_RAS=5cycles
5
6
7
8
9
10
11
12
13
14
15
RDA LAL
l_RCD=1cycle
UA
LA
l_RC=6cycles
DESL
l_RAS=5cycles
RDA LAL
l_RCD=1cycle
UA
LA
DESL
Bank Add.
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
DQ
Hi-Z
(Output)
#0
#0
CL=5
Q0 Q1 Q2 Q3
CL=5
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
DQ
Hi-Z
(Output)
CL=5
Q0 Q1 Q2 Q3
CL=5
Q0 Q1 Q2 Q3
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REV. 0.7 Jan. 2005