K4C89183AF Datasheet, PDF (40/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Multiple Bank Read-Write Timing (BL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
l_RBD=2cycles
WRA LAL RDA LAL
l_WRD=1cycle
UA
LA
UA
LA
Bank
"a"
Bank
"b"
DESL
WRA LAL RDA LAL
l_RWD=3cycles
l_WRD=1cycle
UA
LA
UA
LA
Bank
"c"
Bank
"d"
DESL
WRA LAL RDA LAL
l_RWD=3cycles
l_WRD=1cycle
UA
LA
UA
LA
Bank
"a"
Bank
"b"
l_RC(Bank"a")
l_RC(Bank"a")
Unidirectional DS/QS mode
CL =4
DS
(Input)
QS
Low
(Output)
DQ
Hi-Z
(Output)
WL=3
CL=4
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
CL =5
DS
(Input)
QS
Low
(Output)
DQ
Hi-Z
(Output)
WL=4
CL=5
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
CL =6
DS
(Input)
QS
Low
(Output)
DQ
Hi-Z
(Output)
WL=5
Note :I_RC to the same bank must be satisfied.
CL=6
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1
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REV. 0.7 Jan. 2005