K4C89183AF Datasheet, PDF (47/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Auto-Refresh Timing (CL=4, BL=4)
Unidirectional DS/QS mode
0
1
2
3
4
CLK
CLK
l_RC=5cycles
Command
RDA
LAL
DESL
5
6
WRA REF
7
n-1
n
l_REFC=19cycles
DESL
n+1
n+2
RoDrA
LAL or
MRS or
WRA REF
Bank, Address
Bank,
UA
LA
QS
(output)
l_RCD=1cycle
Low
DQ ^Hi-Z
(output)
l_RAS=4cycles
CL=4
Unidirectional DS/Free Running QS mode
CLK
CLK
l_RC=5cycles
Command
RDA
LAL
DESL
l_RCD=1cycle
Low
Hi-Z
Q0 Q1 Q2 Q3
WRA REF
l_REFC=19cycles
DESL
RoDrA
LAL or
MRS or
WRA REF
Bank, Address
Bank,
UA
LA
QS
(output)
l_RCD=1cycles
l_RAS=4cycles
l_RCD=1cycles
DQ ^Hi-Z
(output)
CL=4
Hi-Z
Q0 Q1 Q2 Q3
Note : In case of CL=4, I_REFC must be meet 19 clock cycles.
When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command
specified by t_REFI must be satisfied.
t_REFI is average interval time in 8 Refresh cycles that is sampled randomly.
CLK
t₁
WRA REF
t₂
WRA REF
t₃
WRA REF
t₇
t₈
WRA REF
WRA REF
8 Refresh cycle
t_{REFI =} ^{Total time of 8 Refresh cycle} ₌ ^{t1+t2+t3+t4+t5+t6+t7+t8}
8
8
t_REFI is specified to avoid partly concentrated current of Refresh operation that is acivated
larger are than Read/Write operation.
- 47 -
REV. 0.7 Jan. 2005