K4C89183AF Datasheet, PDF (25/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Timing Diagrams
Single Bank Read Timing (CL=4)
0
1
2
3
4
5
CLK
CLK
l_RC=5cycles
6
7
8
l_RC=5cycles
9
10
11
12
13
14
15
l_RC=5cycles
Command
RDA LAL
l_RCD=1cycle
DESL
l_RAS=4cycles
RDA LAL
l_RCD=1cycle
DESL
l_RAS=4cycles
RDA LAL
l_RCD=1cycle
DESL
l_RAS=4cycles
RDA
Address
UA
LA
UA
LA
UA
LA
UA
Bank Add.
#0
Unidirectional DS/QS mode
DS
(Input)
QS
(Output)
Low
DQ
Hi-Z
(Output)
CL=4
Unidirectional DS/Free Running QS mode
DS
(Input)
QS
(Output)
DQ
Hi-Z
(Output)
CL=4
#0
#0
#0
CL=4
CL=4
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
CL=4
CL=4
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
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REV. 0.7 Jan. 2005