K4C89183AF Datasheet, PDF (43/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Power Down Timing (CL=4, BL=4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1 n+2 n+3
CLK
CLK
BL=2, SEQUENTIAL MODE
Command
RDA LAL
DESL
DESL
RoDrA
WRA
I_PDA
Address
UA
LA
UA
t_IH
t_IS IPD=2 cycle
PD
Unidirectional DS/QS mode
t_QPDH
I_RC(min), t_REFI(max)
t_PDEX
DS
(input)
QS
(Output)
Low
CL=4
DQ
Hi-Z
(Output)
Q0 Q1 Q2 Q3
Hi-Z
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=4
DC
Hi-Z
(Output)
Q0 Q1 Q2 Q3
Hi-Z
Power Down Entry
Note : PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within t_REFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied I_PDA cycles later.
Power Down Exit
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REV. 0.7 Jan. 2005