K4C89183AF Datasheet, PDF (35/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Multiple Bank Read Timing (CL=5)
CLK
CLK
Command
0
1
2
3
l_RBD=2cycles
RDA LAL RDA LAL
4
5
6
7
8
9
10
11
12
13
14
15
DESL
l_RBD=2cycles
l_RBD=2cycles
l_RBD=2cycles
l_RBD=2cycles
RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank Add.
Bank
"a"
Unidirectional DS/QS mode
Bank
"b"
Bank
"a"
l_RC(Bank"a")=6cycles
l_RC(Bank"6")=6cycles
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
DS
(input)
QS
Low
(Output)
DQ
Hi-Z
(Output)
CL=5
CL=5
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DQ
Hi-Z
(Output)
CL=5
CL=5
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Note : l_RC to the same bank must be satisfied
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REV. 0.7 Jan. 2005