K4C89183AF Datasheet, PDF (50/55 Pages) Samsung semiconductor – 288Mb x18 Network-DRAM2 Specification

K4C89183AF
Command Functions and Operations
K4C89093AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation
mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out
sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after
CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank
goes back automatically to the idle state after I_RC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is
latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be
asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst
length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automat-
ically to the idle state after I_RC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C89093AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to
the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In
a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of
the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is
specified by I_REFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distrib-
uted refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random
distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words,
the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.
Power Down Mode( PD="L" )
When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89183AF become Power Down Mode by asserting
PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore,
the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued
for I_PDA cycle after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a
point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the
RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1
address inputs. The K4C89183AF have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended
Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read
or write cycle. The Regular Mode Register has four function fields.
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REV. 0.7 Jan. 2005