HD64F3694HV Datasheet, PDF (99/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The
subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Figure 5.1 shows a block diagram of the clock pulse generators.
OSC₁
OSC₂
System
clock
oscillator
φ_OSC
(f_OSC)
Duty
correction
circuit
φ_OSC
(f_OSC)
System clock pulse generator
System
clock
divider
φ_OSC
φ_OSC/8
φ_OSC/16
φ_OSC/32
φ_OSC/64
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
Subclock
X₁
oscillator
φ_W
X₂
(f_W)
Subclock pulse generator
Subclock
divider
φ_W/2
φ_W/4
φ_W/8
φ_SUB
Prescaler W
(5 bits)
φ_W/8
to
φ_W/128
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φ_SUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2, and the
subclock is divided by prescaler W to become a clock signal from φw/128 to φw/8. Both the
system clock and subclock signals are provided to the on-chip peripheral modules.
CPG0200A_000020020200
Rev.5.00 Nov. 02, 2005 Page 69 of 418
REJ09B0028-0500