HD64F3694HV Datasheet, PDF (442/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Item
Section 5 Clock Pulse
Generators
Figure 5.3 Typical
Connection to Crystal
Resonator
Figure 5.5 Typical
Connection to Ceramic
Resonator
Page Revision (See Manual for Details)
70
C₁
OSC 1
OSC 2
C₂
C₁ = C₂₂ = 10 to 22 pF
71
C₁
OSC₁
OSC₂
C₂
C₁ = 5 to 30 pF
C₂ = 5 to 30 pF
Section 6 Power-Down 76
Modes
6.1.1 System Control
Register 1 (SYSCR1)
Bit Bit Name Description
3 NESEL Noise Elimination Sampling Frequency
Select
The subclock pulse generator generates the
watch clock signal (φ_W) and the system clock
pulse generator generates the oscillator
clock (φ_OSC). This bit selects the sampling
frequency of the oscillator clock when the
watch clock signal (φ_W) is sampled. When
φ_OSC = 4 to 20 MHz, clear NESEL to 0.
Section 8 RAM
107 ^{Note: * When the E7 or E8 is used, area H'F780 to H'FB7F}
must not be accessed.
Section 13 Watchdog
184
Timer
13.2.1 Timer
Control/Status Register
WD (TCSRWD)
Bit Bit Name Description
4
TCSRWE Timer Control/Status Register WD Write Enable
Rev.5.00 Nov. 02, 2005 Page 412 of 418
REJ09B0028-0500