HD64F3694HV Datasheet, PDF (204/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 12 Timer W
12.5 Operation Timing
12.5.1 TCNT Count Timing
Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure
12.15 shows the timing when the external clock source is selected. The pulse width of the external
clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted
correctly.
φ
Internal
clock
Rising edge
TCNT input
clock
TCNT
N
N+1
N+2
Figure 12.14 Count Timing for Internal Clock Source
φ
External
clock
TCNT input
clock
TCNT
Rising edge
N
Rising edge
N+1
N+2
Figure 12.15 Count Timing for External Clock Source
12.5.2 Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when
TCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TIOR is output at the compare match output pin (FTIOA,
FTIOB, FTIOC, or FTIOD).
When TCNT matches GR, the compare match signal is generated only after the next counter clock
pulse is input.
Rev.5.00 Nov. 02, 2005 Page 174 of 418
REJ09B0028-0500