HD64F3694HV Datasheet, PDF (25/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 254
Figure 15.12 Slave Receive Mode Operation Timing (2)........................................................... 254
Figure 15.13 Clocked Synchronous Serial Transfer Format....................................................... 255
Figure 15.14 Transmit Mode Operation Timing......................................................................... 256
Figure 15.15 Receive Mode Operation Timing .......................................................................... 257
Figure 15.16 Block Diagram of Noise Conceler......................................................................... 257
Figure 15.17 Sample Flowchart for Master Transmit Mode....................................................... 258
Figure 15.18 Sample Flowchart for Master Receive Mode ........................................................ 259
Figure 15.19 Sample Flowchart for Slave Transmit Mode......................................................... 260
Figure 15.20 Sample Flowchart for Slave Receive Mode .......................................................... 261
Figure 15.21 The Timing of the Bit Synchronous Circuit .......................................................... 263
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................... 266
Figure 16.2 A/D Conversion Timing .......................................................................................... 272
Figure 16.3 External Trigger Input Timing ................................................................................ 273
Figure 16.4 A/D Conversion Accuracy Definitions (1) .............................................................. 275
Figure 16.5 A/D Conversion Accuracy Definitions (2) .............................................................. 275
Figure 16.6 Analog Input Circuit Example................................................................................. 276
Section 17 EEPROM
Figure 17.1 Block Diagram of EEPROM ................................................................................... 278
Figure 17.2 EEPROM Bus Format and Bus Timing .................................................................. 280
Figure 17.3 Byte Write Operation .............................................................................................. 283
Figure 17.4 Page Write Operation .............................................................................................. 284
Figure 17.5 Current Address Read Operation............................................................................. 285
Figure 17.6 Random Address Read Operation ........................................................................... 286
Figure 17.7 Sequential Read Operation (when current address read is used)............................. 287
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Figure 18.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 290
Figure 18.2 Operational Timing of Power-On Reset Circuit...................................................... 294
Figure 18.3 Operational Timing of LVDR Circuit ..................................................................... 295
Figure 18.4 Operational Timing of LVDI Circuit....................................................................... 296
Figure 18.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 297
Section 19 Power Supply Circuit
Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 299
Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 300
Section 21 Electrical Characteristics
Figure 21.1 System Clock Input Timing..................................................................................... 351
Figure 21.2 RES Low Width Timing.......................................................................................... 352
Rev.5.00 Nov. 02, 2005 Page xxiii of xxviii