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| HD64F3694HV Datasheet, PDF (132/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series | |||
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Section 7 ROM
Increment address
Erase start
SWE bit â 1
Wait 1 µs
nâ1
Set EBR1
Enable WDT
ESU bit â 1
Wait 100 µs
E bit â 1
Wait 10 ms
E bit â 0
Wait 10 µs
ESU bit â 10
10 µs
Disable WDT
EV bit â 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
*
Read verify data
No
Verify data + all 1s ?
Yes
No
Last address of block ?
Yes
EV bit â 0
Wait 4 µs
EV bit â 0
Wait 4µs
nân+1
No
All erase block erased ?
Yes
Yes
SWE bit â 0
Wait 100 µs
Yes
n â¤100 ?
No
SWE bit â 0
Wait 100 µs
End of erasing
Erase failure
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
Rev.5.00 Nov. 02, 2005 Page 102 of 418
REJ09B0028-0500
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