HD64F3694HV Datasheet, PDF (266/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 15 I²C Bus Interface 2 (IIC2)
15.3.2 I²C Bus Control Register 2 (ICCR2)
ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the control part of the I²C bus interface 2.
Initial
Bit
Bit Name Value R/W Description
7
BBSY
0
R/W Bus Busy
This bit enables to confirm whether the I²C bus is
occupied or released and to issue start/stop conditions in
master mode. With the clocked synchronous serial
format, this bit has no meaning. With the I²C bus format,
this bit is set to 1 when the SDA level changes from high
to low under the condition of SCL = high, assuming that
the start condition has been issued. This bit is cleared to
0 when the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop condition
has been issued. Write 1 to BBSY and 0 to SCP to issue
a start condition. Follow this procedure when also re-
transmitting a start condition. Write 0 in BBSY and 0 in
SCP to issue a stop condition. To issue start/stop
conditions, use the MOV instruction.
6
SCP
1
W
Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in SCP.
A retransmit start condition is issued in the same way. To
issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not
stored.
5
SDAO
1
R/W SDA Output Value Control
This bit is used with SDAOP when modifying output level
of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
Rev.5.00 Nov. 02, 2005 Page 236 of 418
REJ09B0028-0500