HD64F3694HV Datasheet, PDF (194/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 12 Timer W
Initial
Bit
Bit Name Value R/W Description
1
IOC1
0
R/W I/O Control C1 and C0
0
IOC0
0
R/W When IOC2 = 0,
00: No output at compare match
01: 0 output to the FTIOC pin at GRC compare match
10: 1 output to the FTIOC pin at GRC compare match
11: Output toggles to the FTIOC pin at GRC compare
match
When IOC2 = 1,
00: Input capture to GRC at rising edge of the FTIOC pin
01: Input capture to GRC at falling edge of the FTIOC pin
1X: Input capture to GRC at rising and falling edges of
the FTIOC pin
Legend: X: Don't care.
12.3.7 Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to
CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting
the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF
flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is
generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.
TCNT is initialized to H'0000 by a reset.
12.3.8 General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an output-
compare register or an input-capture register. The function is selected by settings in TIOR0 and
TIOR1.
When a general register is used as an input-compare register, its value is constantly compared with
the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA,
IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when
IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TCNT value is stored in the general register. The corresponding flag
(IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit
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