HD64F3694HV Datasheet, PDF (289/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 15 I²C Bus Interface 2 (IIC2)
Mater receive mode
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
Dummy-read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Last receive ^Yes
- 1?
No
Read ICDRR
Set ACKBT in ICIER to 1
Set RCVD in ICCR1 to 1
Read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Clear STOP in ICSR
Write 0 to BBSY
and SCP
Read STOP in ICSR
No
STOP=1 ?
Yes
Read ICDRR
Clear RCVD in ICCR1 to 0
[1] Clear TEND, select master receive mode, and then clear TDRE.*
[2] Set acknowledge to the transmit device.*
[1]
[3] Dummy-read ICDDR.*
[2]
[4] Wait for 1 byte to be received
[5] Check whether it is the (last receive - 1).
[3]
[6] Read the receive data last.
[7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[4]
[8] Read the (final byte - 1) of receive data.
[9] Wait for the last byte to be receive.
[5]
[10] Clear STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[7]
[14] Clear RCVD.
[8]
[15] Set slave receive mode.
[9]
[10]
[11]
[12]
[13]
[14]
Clear MST in ICCR1 to 0
End
[15]
Note: Do not activate an interrupt during the execution of steps [1] to [3].
Supplementary explanation: When one byte is received, steps [2] to [6] are
skipped after step [1], before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Figure 15.18 Sample Flowchart for Master Receive Mode
Rev.5.00 Nov. 02, 2005 Page 259 of 418
REJ09B0028-0500