HD64F3694HV Datasheet, PDF (35/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 1 Overview
Subclock
generator
System
clock
generator
P10/TMOW
P11
P12
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
P20/SCK3
P21/RXD
P22/TXD
SDA
SCL
CPU
H8/300H
Data bus (lower)
ROM
RAM
Timer W
SCI3
Timer A
Watchdog
timer
Timer V
IIC2
A/D
converter
POR/LVD
(optional)
Data bus (upper)
Address bus
EEPROM
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P74/TMRIV
P75/TMCIV
P76/TMOV
P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTRG
P56/SDA
P57/SCL
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
AVCC
Note: The HD64N3694G is a stacked-structure product in which an EEPROM chip is mounted on the HD64F3694G (F-ZTAT^TM version).
The HD6483694G is a stacked-structure product in which an EEPROM chip is mounted on the HD6433694G (mask-ROM version).
Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version)
Rev.5.00 Nov. 02, 2005 Page 5 of 418
REJ09B0028-0500